1. Field of the Invention
This invention relates to integrated circuit design methodologies and, more particularly, to methodologies for architectural power estimation.
2. Description of the Related Art
Improvements in integrated circuit manufacturing technology have resulted in steady and dramatic increases in integrated circuit performance, particularly in terms of clock speeds. Historically, microprocessor clock speeds have doubled every two to three years, and feature size reductions have enabled the number of devices per unit of circuit area to keep pace. However, such advances have come at the cost of similarly dramatic increases in integrated circuit power consumption. Increases in clock speeds have not been offset by decreases in operating voltage and total circuit size. Further, to achieve higher clock speeds, faster transistor designs are frequently employed, which offer increased switching speed at the expense of increased leakage current (i.e., power consumed even when the transistor is not switching).
Increased integrated circuit power consumption directly affects the cost of building a system including such circuits. As power consumption increases, more costly cooling systems such as larger fans, heat sinks, and refrigeration must be employed to remove excess heat from the system and prevent integrated circuit failure. However, intense system price competition in high-volume market segments often limits the budget available for cooling systems. Increasingly, integrated circuits are at risk of becoming thermally constrained—forced to run at less than their designed operating frequency due to an inability to sufficiently cool the circuit at that frequency.
Given a particular clock frequency design goal and a particular design process voltage, power consumption can only be mitigated through careful integrated circuit design. For example, circuit structures unused during a given clock cycle may be disabled, and the global integrated circuit floorplan may be optimized to reduce the lengths (and thus the total capacitance) of wide buses. However, accurately estimating the impact of such approaches on actual circuit power consumption is difficult. Current techniques for power estimation require detailed circuit schematics, design code (such as register transfer language (RTL) code), and a floorplan from which to extract circuit geometries and bus lengths. Current power estimation tools are slow due to the amount of design detail they must take into account, which consequently limits the number of representative execution workloads that can be analyzed to assess power consumption.
As a result, for current techniques power estimation occurs very late in the integrated circuit development cycle, after a substantial amount of design work has been completed. Further, the accuracy of current techniques of power estimation is constrained by the limited amount of analysis that can be performed, increasing the risk that the effect of some power-intensive workloads may be overlooked. Consequently, integrated circuit architects and designers do not have the opportunity to analyze and select the appropriate design tradeoffs and optimizations at the beginning of the development cycle, when rework is least expensive. Current power estimation techniques result in longer development cycles, increased design resource requirements, and increased risk that an integrated circuit may not meet its design and marketing goals, all contributing to the expense of the integrated circuit design process.